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supertex inc. supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com hv5308b features processed with hvcmos ? technology low power level shifting source/sink current minimum 20ma shift register speed 8.0mhz latched data outputs cmos compatible inputs forward and reverse shifting options diode to vpp allows ef?cient power recovery ? ? ? ? ? ? ? ? general description the hv5308b is a low voltage serial to high voltage parallel converter with push-pull outputs. this device has been designed for use as a driver for ac-electroluminescent displays. it can also be used in any application requiring multiple output high voltage current sourcing and sinking capabilities, such as driving plasma panels, vacuum ?uorescent, or large matrix lcd displays. the hv5308b consists of a 32-bit shift register, 32 latches, and control logic to enable outputs. q1 is connected to the ?rst stage of the shift register through the output enable logic. data is shifted through the shift register on the low to high transition of the clock. when viewed from the top of the package, the hv5308b shifts in the clockwise direction. a data output buffer is provided for cascading devices. this output re?ects the current status of the last bit of the shift register (32). operation of the shift register is not affected by the le (latch enable) or the oe (output enable) inputs. transfer of data from the shift register to the latch occurs when the le input is high. the data in the latch is retained when le is low. typical application circuit 32-channel serial to parallel converter with high voltage push-pull outputs da ta input clk le oe hv out 1 micr o processor supertex hv5308b display panel columns row driver hv out 32 data input for cascading the next hv5308b da ta out low v oltage high v oltage shift register latches output contr . level tr anslators & push-pull output buffers v pp v dd
2 hv5308b supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com ordering information device package options 44-lead quad cerpac .650x.650in body .190in height (max) .050in pitch 44-lead pqfp 10.00x10.00mm body 2.35mm height (max) 0.80mm pitch 44-lead plcc .653x.653in body .180in height (max) .050in pitch hv5308b hv5308dj-b* hv5308pg-b-g HV5308PJ-B-G -g indicates package is rohs compliant (green). * hi-rel process ?ow available. absolute maximum ratings supply voltage, v dd -0.5v to +16v supply voltage, v pp -0.5v to +90v logic input levels -0.5v to v dd +0.5v ground current 1 1.5a continuous total power dissipation 2 plastic ceramic 1200mw 1500mw operating temperature range plastic ceramic -40 o c to +85 o c -55 o c to +125 o c storage temperature range -65 o c to +150 o c lead temperature 3 260 o c parameter value pin con?gurations notes: duty cycle is limited by the total power dissipated in the package. for operation above 25c ambient derate linearly to maximum operating temperature at 20mw/c for plastic and at 15mw/c for ceramic. 1.6mm (1/16 inch) from case for 10 seconds 1. 2. 3. 1 44 6 40 1 44 product marking absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. yy = year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = green packagin g *may be part of top markin g top marking bottom marking y y w w hv5308pg-b l l l l l l l l l cccccccc aa a yy = year sealed ww = week sealed l = lot number a = assembler id c = country of origin* = green packagin g *may be part of top marking top marking bottom marking yyww aaa hv5308pj lllllllll l ccccccccccc 44-lead pqfp (pg) (top view) 44-lead plcc (pj) (top view) 44-lead pqfp (pg) 44-lead plcc (pj) 1 44 6 40 44-lead quad cerpac (dj) (top view) yy = year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* *may be part of top marking top marking bottom marking yyww hv5308dj- b llllllllll ccccccccccc aaa 44-lead quad cerpac (dj) packages may or may not include the following marks: si or
3 hv5308b supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com sym parameter min max units conditions electrical characteristics (v pp = 60v, v dd = 12v, t a = 25c) dc characteristics i pp v pp supply current - 0.5 ma hv outputs high to low i ddq i dd supply current (quiescent) - 100 a all inputs = v dd or gnd i dd i dd supply current (operating) - 15 ma v dd = v dd max, f clk = 8.0mhz v oh (data) shift register output voltage 10.5 - v i o = -100a v ol (data) shift register output voltage - 1.0 v i o = 100a i ih current leakage, any input - 1.0 a v in = v dd i il current leakage, any input - -1.0 a v in = 0 v oc hv output clamp diode voltage - -1.5 v i ol = -100ma v oh hv output when sourcing 52 - v i oh = -20ma, -40 to 85c v ol hv output when sinking - 8.0 v i ol = 20ma, -40 to 85c v oh hv output when sourcing 52 - v i oh = -15ma, -55 to 125c v ol hv output when sinking - 8.0 v i ol = 15ma, -55 to 125c power-up sequence power-up sequence should be the following: connect ground apply v dd set all inputs (data, clk, le, etc.) to a known state apply v pp the v pp should not fall below v dd or ?oat during operation. power-down sequence should be the reverse of the above. 1. 2. 3. 4. 5. sym parameter min max units recommended operating conditions (over -40c to 85c for plastic and -55c to 125c for ceramic) v dd logic voltage supply 10.8 13.2 v v pp high voltage supply 8.0 80 v v ih input high voltage v dd - 2.0 v dd v v il input low voltage 0 2.0 v f clk clock frequency 0 8.0 mhz
4 hv5308b supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com switching waveforms le hv ou t w/ s/r lo w data valid 50 % data inpu t cl k data ou t t su t h t wl t wh 50 % 50 % t dl h t dh l 50 % t wle t dl e t sl e 50 % 50 % t on 10 % 90 % 90 % 10 % t of f v ih v il v ih v il v oh v ol v oh v ol v ih v il v oh v ol v oh v ol 50 % 50 % 50 % 50 % hv ou t w/ s/r high ac characteristics sym parameter min max units conditions f clk clock frequency - 8.0 mhz --- t wl or t wh clock width, high or low 62 - ns --- t su setup time before clk rises 25 - ns --- t h hold time after clk rises 10 - ns --- t dlh (data) data output delay after l to h clk - 110 ns c l = 15pf t dhl (data) data output delay after h to l clk - 110 ns c l = 15pf t dle le delay after l to h clk 50 - ns --- t wle width of le pulse 50 - ns --- t sle le setup time before l to h clk 50 - ns --- t on delay from le to hv out , l to h - 500 ns --- t off delay from le to hv out , h to l - 500 ns ---
5 hv5308b supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com functional block diagram v pp le oe hv ou t 2 ? ? ? 28 additional output s ? ? ? hv ou t 31 hv ou t 1 hv ou t 32 data input cl k data out 32 bit static registe r 32 bit latches data input le oe hv out x x l all hv out = low x l h previous latched data h h h h l h h l function tables data input clk* data out h h l l x no no change note: * = low - to - high transition h = high l = low x = dont care input and output equivalent circuits vdd data input gnd vpp gnd hv ou t logic inputs gnd data out logic data output high voltage outputs vdd
6 hv5308b supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com pin # function description 1 hv out 22 high voltage outputs. high voltage push-pull outputs, which, depending on controlling low voltage data, can drive loads either to gnd, or to v pp rail levels. 2 hv out 21 3 hv out 20 4 hv out 19 5 hv out 18 6 hv out 17 7 hv out 16 8 hv out 15 9 hv out 14 10 hv out 13 11 hv out 12 12 hv out 11 13 hv out 10 14 hv out 9 15 hv out 8 16 hv out 7 17 hv out 6 18 hv out 5 19 hv out 4 20 hv out 3 21 hv out 2 22 hv out 1 23 data out serial data output. data output for cascading to the data input of the next device. 24 n/c no connect. 25 26 27 clk data shift register clock input are shifted into the shift register on the positive edge of the clock. 28 gnd logic and high voltage ground 29 vpp high voltage power rail. 30 vdd low voltage logic power rail. 44-lead pqfp pin assignment (pg)
7 hv5308b supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com pin # function description 31 le latch enable input. when le is high, shift register data is transferred into a data latch. when le is low, data is latched, and new data can be clocked into the shift register. 32 data input serial data input. data needs to be present before each rising edge of the clock. 33 oe output enable input. when oe is low, all hv outputs are forced into a low state, regardless of data in each channel. when oe is high, all hv outputs re?ect data latched. 34 n/c no connect. 35 hv out 32 high voltage outputs. high voltage push-pull outputs, which, depending on controlling low voltage data, can drive loads either to gnd, or to v pp rail levels. 36 hv out 31 37 hv out 30 38 hv out 29 39 hv out 28 40 hv out 27 41 hv out 26 42 hv out 25 43 hv out 24 44 hv out 23 44-lead pqfp pin assignment (pg)
8 hv5308b supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com 44-lead quad cerpac/plcc pin assignment (dj/pj) pin # function description 1 hv out 17 high voltage outputs. high voltage push-pull outputs, which, depending on controlling low voltage data, can drive loads either to gnd, or to v pp rail levels. 2 hv out 16 3 hv out 15 4 hv out 14 5 hv out 13 6 hv out 12 7 hv out 11 8 hv out 10 9 hv out 9 10 hv out 8 11 hv out 7 12 hv out 6 13 hv out 5 14 hv out 4 15 hv out 3 16 hv out 2 17 hv out 1 18 data out serial data output. data output for cascading to the data input of the next device. 19 n/c no connect. 20 21 22 clk data shift register clock input are shifted into the shift register on the positive edge of the clock. 23 gnd logic and high voltage ground 24 vpp high voltage power rail. 25 vdd low voltage logic power rail. 26 le latch enable input. when le is high, shift register data is transferred into a data latch. when le is low, data is latched, and new data can be clocked into the shift register. 27 data input serial data input. data needs to be present before each rising edge of the clock.
9 hv5308b supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com pin # function description 28 oe output enable input. when oe is low, all hv outputs are forced into a low state, regardless of data in each channel. when oe is high, all hv outputs re?ect data latched. 29 n/c no connect. 30 hv out 32 high voltage outputs. high voltage push-pull outputs, which, depending on controlling low voltage data, can drive loads either to gnd, or to v pp rail levels. 31 hv out 31 32 hv out 30 33 hv out 29 34 hv out 28 35 hv out 27 36 hv out 26 37 hv out 25 38 hv out 24 39 hv out 23 40 hv out 22 41 hv out 21 42 hv out 20 43 hv out 19 44 hv out 18 44-lead quad cerpac/plcc pin assignment (dj/pj)
10 hv5308b supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com 44-lead quad cerpac package outline (dj) .650x.650in body, .190in height (max), .050in pitch .150 ma x .040 x 45 o 1 .075 ma x 6 40 d d1 e1 e to p v iew v iew b a a2 a1 seating plane e b note 1 (index area) .035 x 45 o 0.25 max 3 places .025 mi n vi ew b 44 b1 horizontal side v iew ve rtical side v iew symbol a a1 a2 b b1 d d1 e e1 e dimension (inches) min .155 .090 .060 ref .017 .026 .685 .630 .685 .630 .050 bsc nom .172 .100 .019 .029 .690 .650 .690 .650 max .190 .120 .021 .032 .695 .665 .695 .665 jedec registration mo-087, variation ab, issue b, august, 1991. drawings not to scale . supertex doc. #: dspd-44cerpacdj, version d090808. note: a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. 1.
11 hv5308b supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com 44-lead pqfp package outline (pg) 10.00x10.00mm body, 2.35mm height (max), 0.80mm pitch symbol a a1 a2 b d d1 e e1 e l l1 l2 dimension (mm) min 1.95* 0.00 1.95 0.30 13.65* 9.80* 13.65* 9.80* 0.80 bsc 0.73 1.95 ref 0.25 bsc 0 o nom - - 2.00 - 13.90 10.00 13.90 10.00 0.88 3.5 o max 2.35 0.25 2.10 0.45 14.15* 10.20* 14.15* 10.20* 1.03 7 o jedec registration mo-112, variation aa-2, issue b, sep.1995. * this dimension is not speci?ed in the jedec drawing. drawings not to scale. supertex doc. #: dspd-44pqfppg, version c041309. 1 44 seating plane gauge plane l l1 l2 vi ew b vi ew b seating plane top view d d1 e e1 b e side view a2 a a1 note 1 (index area d1/4 x e1/4) note: a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. 1.
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate product liability indemnification insurance agreement. supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry an d specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//ww w. supertex.com ) ?2010 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 te l: 408-222-8888 www .supertex.com 12 hv5308b (the package drawing(s) in this data sheet may not re?ect the most current speci?cations. for the latest package outline information go to http://www. supertex.com/packaging.htm l .) doc.# dsfp-hv5308b b021610 44-lead plcc package outline (pj) .653x.653in body, .180in height (max), .050in pitch symbol a a1 a2 b b1 d d1 e e1 e dimension (inches) min .165 .090 .062 .013 .026 .685 .650 .685 .650 .050 bsc nom .172 .105 - - - .690 .653 .690 .653 max .180 .120 .083 .021 .036 ? .695 .656 .695 .656 jedec registration ms-018, variation ac, issue a, june, 1993. ? this dimension differs from the jedec drawing. drawings not to scale. supertex doc. #: dspd-44plccpj, version e041309. .150 ma x .048/.042 x 45 o 1 .075 ma x 6 40 d d1 e1 e to p v iew horizontal side v iew v iew b a a2 a1 seating plane e b note 1 (index area) .056/.042 x 45 o .020max (3 places) .020 min ve rtical side v iew v iew b note 2 44 b1 base plane notes: a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. actual shape of this feature may vary. 1. 2.

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